The present invention relates to a semiconductor integrated circuit including a standard cell, a standard cell layout design method, and a layout design software product stored in a computer-readable recording medium.
In layout design of a semiconductor integrated circuit, a method of laying out standard cells having a predetermined height in the vertical direction (row direction) is employed.
FIG. 10 shows the structure of a typical standard cell. This standard cell has an inverter circuit structure including one p-channel transistor and one n-channel transistor. A gate electrode G, an n-well W1 in which a p-channel transistor is formed, and a p-well W2 in which an n-channel transistor is formed are laid out in correspondence with a planar structure formed on the surface portion of a semiconductor substrate. A space ha necessary in terms of design rules is present at the well boundary between the n-well W1 and the p-well W2.
When only logic is taken into consideration, the chip area can be reduced by making each standard cell small. Hence, the total area of a chip can be reduced by forming a standard cell having a small height.
In this case, however, the driving capability of one standard cell is low. To form a standard cell with a high driving capability, standard cells SC1 must be arrayed vertically in a plurality of stages, as shown in FIG. 11. As a circuit, inverters having identical structures are connected in parallel.
As described above, the space ha is necessary at the well boundary. This decreases the efficiency of the area usable as transistors. The more the standard cells stacked in the vertical direction, the larger the space ha becomes.
When a height h1 of the standard cell is set small, the height in the vertical direction can be suppressed small. However, the length in the horizontal direction must be increased. A cell having a small height and a large width is not preferable from the viewpoint of the degree of freedom in standard cell layout in a chip. Hence, there is a limitation on suppressing the height h1.
Conventionally, standard cells having one kind of vertical height (h1) are laid out. As shown in FIG. 12, one row region includes a structure having two stages of standard cells SC1 stacked vertically, a structure having one stage of standard cell SC1, and a structure having three stages of standard cells SC1. Hence, bent portions R1 and R2 form which connect a power supply voltage line Vcc and a ground voltage line Vss arranged on the upper and lower sides of the row region to the cells in different numbers of stages, resulting in a waste of area.
As described above, conventionally, standard cells having one kind of vertical height are stacked in a plurality of stages in accordance with the driving capability. Accordingly, the area efficiency decreases.